Skah T
Former VML engineer
- Reaction score
- 62
While reading this article about the Cell architecture I'm reminded quite a bit of the Aries MPE architecture. In particular is this sections describing the individual SPEs. I added translation from Cell to NUON world in color.
You could be reading the NUON architecture manual. In fact it just struck me that experience programming for NUON would translate well to Cell. Mabye I should check around for PS3 developers
One area where NUON still has the edge in being able to execute up to seven ops per clock cycle rather than just two on the Cell's SPEs.
Unlike the PPE [MPE3], the SPEs [MPEs 0-2] do not have caches. Instead, they each get a 256K [4-8K] "local store" that only they can see. All code and data for the SPE [MPE] must be stored within this 256K [4-8K] local area. In fact, the SPEs [MPEs] cannot "see" the rest of the chip's address space at all. They can't access each others' local stores nor can they access the PPE's [MPE3's] caches or other on-chip or off-chip resources. In effect, each SPE is blind and limited to just its own little corner of the Cell [Aries] world.
Why the crippled address map? Each SPE [MPE] is limited to just a single memory bank with deterministic access characteristics in order to guarantee its performance. Off-chip (or even on-chip) memory accesses take time--sometimes an unpredictable amount of time, and that goes against the SPE's [MPE's] purpose. They're designed to be ultra-fast and ultra-reliable units for processing streaming media, often in real-time situations where the data can't be retransmitted. By limiting their options and purpose, Cell's [Aries'] designers gave the SPEs [MPEs] deterministic performance.
You could be reading the NUON architecture manual. In fact it just struck me that experience programming for NUON would translate well to Cell. Mabye I should check around for PS3 developers
One area where NUON still has the edge in being able to execute up to seven ops per clock cycle rather than just two on the Cell's SPEs.