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AMD pushes UCIe open chiplet spec to foster custom designs – Board members include Alibaba, Intel, Nvidia, TSMC, and Samsung
Several years ago, AMD adopted a multi-chiplet design for its client desktop and data center processors well ahead of its rivals. Back then, it was the only way for AMD to offer products with higher core counts than rival Intel, and now the move is seen as a strategic pivot towards an inevitable multichiplet design methodology. Today, Sam Naffziger, senior vice president and corporate fellow at AMD, thinks about how the Universal Chiplet Interconnect Express (UCIe) specification will create a chiplet ecosystem and enable custom multi-chiplet design.
For modular multichiplet designs, a high-performance, low-latency, and low-power interface is a must. The Infinity Fabric interface enabled AMD to build unique EPYC, Ryzen, and now Instinct MI300-series processors with unrivaled core counts, performance, and feature sets, Naffziger explained in a YouTube video conversation with Mark Papermaster, AMD's chief technology officer.
"The [interface] latency was too high, the power cost was too high, but we had a team of can-do engineers who said, 'I know how to solve that problem,' 'I will deliver a lightweight interface,' 'I will slim this down,' and 'I will eliminate cycles of latency,'" Naffziger said referring to the era when AMD was developing its multi-chiplet 2nd-gen EPYC and Ryzen processors. "If we hit these targets, now we have a multi-die solution that behaves just like a monolithic SoC. We set those targets, and then we oversaw the team's execution to make it happen. It was so transformative."
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Several years ago, AMD adopted a multi-chiplet design for its client desktop and data center processors well ahead of its rivals. Back then, it was the only way for AMD to offer products with higher core counts than rival Intel, and now the move is seen as a strategic pivot towards an inevitable multichiplet design methodology. Today, Sam Naffziger, senior vice president and corporate fellow at AMD, thinks about how the Universal Chiplet Interconnect Express (UCIe) specification will create a chiplet ecosystem and enable custom multi-chiplet design.
For modular multichiplet designs, a high-performance, low-latency, and low-power interface is a must. The Infinity Fabric interface enabled AMD to build unique EPYC, Ryzen, and now Instinct MI300-series processors with unrivaled core counts, performance, and feature sets, Naffziger explained in a YouTube video conversation with Mark Papermaster, AMD's chief technology officer.
"The [interface] latency was too high, the power cost was too high, but we had a team of can-do engineers who said, 'I know how to solve that problem,' 'I will deliver a lightweight interface,' 'I will slim this down,' and 'I will eliminate cycles of latency,'" Naffziger said referring to the era when AMD was developing its multi-chiplet 2nd-gen EPYC and Ryzen processors. "If we hit these targets, now we have a multi-die solution that behaves just like a monolithic SoC. We set those targets, and then we oversaw the team's execution to make it happen. It was so transformative."
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AMD says the UCIe universal chiplet interface will create a whole ecosystem — custom multi-chiplet designs are the future
AMD pushes UCIe open chiplet spec to foster custom designs – Board members include Alibaba, Intel, Nvidia, TSMC, and Samsung
